Local-area networks (LANs) or communication devices transmitting and receiving digital signals commonly operate on standards such as Ethernet 10BASE-T or 100BASE-TX. The 100BASE-TX Ethernet standard enables communication at 100 Mb/s on unshielded twisted pair (UTP) copper wire by using MLT-3 encoding. MLT-3 encoding transmits "1"s as ordered level changes between 3 levels {1, 0, -1}, whereas "0"s are transmitted as the same level as the previous symbol. Thus the signal 1111111 could be encoded as {0, 1, 0, -1, 0, 1, 0, -1}, and the signal 1111011100 could be encoded as {0, 1, 0, -1, -1, 0, 1, 0, 0, 0}. In principle, other forms of ordered level change encoding can also be used. For example, instead of 3 ordered level changes, signals could also be encoded with 5 ordered level changes {2, 1, 0, -1, -2}.
One of the advantages of ordered level change encoding is that the high frequency components of the signal are reduced. For MLT-3 encoding with signals clocked at a standard rate of 125 MHz (8 ns per symbol), the signal frequency varies from 0, for a run of "0"s, to a maximum of 31.25 MHz (125/4) for a run of "1"s. (125 MHz is a nominal frequency, and in practice the frequency will vary slightly from the nominal.) The relatively low signal frequency is advantageous in reducing electromagnetic interference (EMI) and relaxing frequency-related demands on signal processing equipment and wiring. However, MLT-3 encoding creates inherent problems for receivers, particularly when the receivers are at the end of long runs (of the order of 100 m) of cable, as described hereinbelow.
MLT-3 signals are transmitted and received via transformers, so that there is no path for DC between transmitter and receiver. If a continuous string of "0"s is transmitted, then there may be an effective DC level in the transmitted signal, which needs to be detected by the receiver. At the receiver, the signal is detected by digitizing and comparing the received signal to the receiver's baseline. In order to correctly detect DC levels, the receiver's baseline must be constantly adjusted for baseline wander (BLW)--since BLW or the inaccurate correction thereof causes errors in the recovered signal.
The incoming signal is sampled and digitized by an A/D converter, preferably operating at the minimum theoretical sample rate for the A/D converter, equal to the clock rate of the signal, i.e., the nominal 125 MHz. In order for the A/D converter to operate efficiently, the receiver has to recover the exact clock timing, both in frequency and in phase, from the received signal.
In a paper by Mueller and Muller, "Timing recovery in digital synchronous data receivers," IEEE Transactions on Communications, pp 516-531, Vol. 24, May 1976, which is herein incorporated by reference, the authors propose a timing recovery algorithm. The paper is accepted in the art as the basis for timing recovery algorithms, and relies on selecting a timing function that is zero at an assumed best sampling point. The phase of the sampling point is then adjusted until its phase is zero.
In a paper by Fertner and Solve, "Symbol-rate timing recovery comprising the optimum signal-to-noise ratio in a digital subscriber loop," IEEE Transactions on Communications, pp 925-936, Vol. 45, August 1997, which is herein incorporated by reference, the authors investigate a recovery algorithm that is based on the correlation between a mean-square error from a decision feedback equalizer and an arriving sample signal. The authors also point out practical complications involved in the relatively conceptually straightforward derivation of Mueller and Muller.
FIG. 1 is a graph showing the typical received shape of an 8 ns positive pulse after transmission along different lengths of unshielded twisted pair category 5 (UTP cat-5) cables. The pulse, comprising a sharp leading edge and a less sharp trailing edge, drops in height exponentially, and increases in width with increasing cable length. Consequently, for cable lengths over 100 m, it becomes increasingly difficult to recover the clock and distinguish one pulse from the next.
FIG. 2 shows a composite received signal 11 for a cable 130 m long, given an input signal 13 of 1, 1, 1, 1, 0, -1, 0, 1, wherein 1 corresponds to a positive pulse and -1 corresponds to a negative pulse. The circles on composite graph 11 correspond to measured signals spaced 8 ns apart. This graph illustrates the difficulty of recovering the clock and the input signal values, since the measured values are not simply related to the input signal of 1, 1, 1, 1, 0, -1, 0, 1.
FIG. 3 is a block diagram of a receiver 20 used to detect 100BASE-TX signals of the type shown in FIG. 2, as is at present known in the art. Signals from a magnetics (transformer) stage are input to an automatic gain control (AGC) amplifier 14, and transferred to an analog summer 18, wherein a BLW correction is added. The result is transferred to an A/D converter 21. The A/D converter generates corresponding digital signals, sampled according to an input clock signal from a PLL 40 and phase multiplexer 42, and the digitized signals are transferred to a digital signal processing (DSP) core 48. The clock signal is synchronized in frequency and phase with the incoming input signal, in order to minimize conversion errors in the A/D converter.
DSP core 48 comprises a forward equalization (FEQ) module 26, an adder 28, a decision (DEC) module 30, and a decision feedback equalizer (DFE) module 32, which together act to supply data to a baseline wander correction module 24. BLW correction module 24 supplies the aforementioned (analog) BLW correction signal to summer 18. Typically, the magnetics stage has a non-linear inductance, and acts as a high pass filter, and BLW module 24 comprises a matching low pass filter whose frequency response is adjustable. The characteristics of the low pass filter are pre-adjusted to minimize BLW. The high pass filter characteristics of the magnetics stage, however, depend on the DC current flowing in the magnetics stage, so that the characteristics are not fixed and are difficult to predict.
DSP core 48 also comprises a DSP control 36 and a timing control 38. On the basis of signals output by decision module 30, DSP control 36 supplies data to timing control 38. Timing control 38 controls the frequency and phase of the clock signal supplied by multiolexer 42, for example, according to the aforementioned method of Mueller and Muller. Core 48 transfers the equalized, BLW-corrected signals in MLT-3 format to module 46, wherein the signals are processed further for transmission in binary format, preferably in a non-return-to-zero (NRZ) format.
Other existing receivers use analog equalizers, such as high pass filters; these equalizers inherently enhance the noise at the same time as they enhance the high-frequency gain. Errors in the assumed parameter values of the equalizers lead to an error in reconstructing the BLW. Furthermore, any decision error leads to symbol error and inaccurate BLW correction for a relatively long time period.
In order to overcome the inherent limitations of poor transmission of low frequency signals through the input transformers, existing receivers use complicated adaptive algorithms to reconstruct the transmitted DC level. Existing receivers continuously monitor the signal baseline to correct BLW.